The PID effect analysis experiment is a critical reliability test that evaluates how photovoltaic modules withstand potential induced degradation under high system voltage, elevated temperature, and high humidity. This article explains the PID degradation mechanism, standard test procedures based on IEC TS 62804, key measured parameters, and how test results support module certification, material selection, and solar power plant quality assurance.
Technical Overview
Potential Induced Degradation (PID) is one of the most significant field-reliability risks for photovoltaic modules operating in high-voltage grid-connected systems. In a series-connected string, the module frame is typically grounded, while individual cells may sit several hundred to fifteen hundred volts above or below ground potential. This sustained voltage difference drives small leakage currents through the encapsulant, front glass, and cell surfaces, gradually degrading the electrical performance of the module. In severe cases, PID can reduce module power output by 30 percent or more, directly impacting the energy yield and financial return of a solar power plant.
The dominant failure mode in conventional p-type crystalline silicon modules is PID-s, a shunting-type degradation in which sodium ions from soda-lime front glass migrate under the electric field, penetrate the silicon nitride anti-reflective coating, and create shunt paths across the p-n junction. This causes a collapse of shunt resistance and fill factor, visible as dark patterns in electroluminescence (EL) imaging. A second mechanism, PID-c, involves sodium decoration of crystal defects such as stacking faults and tends to produce more permanent damage. Positive-bias polarization effects are also observed in certain n-type and older module designs. PID susceptibility depends on temperature, humidity, voltage magnitude and polarity, grounding configuration, cell emitter and anti-reflective coating design, encapsulant volume resistivity, and glass composition.
A PID effect analysis experiment reproduces these stress conditions in a controlled laboratory environment in accordance with IEC TS 62804-1 and the PID test sequence MQT 21 of IEC 61215, allowing manufacturers, certification bodies, and plant owners to quantify degradation severity and verify anti-PID design measures.
Testing Samples
Crystalline Silicon PV Modules
Full-size crystalline silicon modules of all mainstream cell technologies, including PERC, TOPCon, HJT, and Al-BSF, represent the primary test population. P-type modules are typically tested under negative bias, which represents the worst-case condition in transformerless systems with the negative pole effectively floating. Small-area coupons and two-cell mini-modules are also widely used for research-grade mechanism studies.
Thin-Film PV Modules
CIGS, CdTe, and amorphous silicon thin-film products can also exhibit PID-type degradation, and their evaluation follows the corresponding methodologies described in IEC TS 62804-2, with attention to TCO corrosion and transparent conductive layer stability.
Bifacial, Double-Glass, and Frameless Modules
Glass-glass constructions, frameless laminates, and modules with barrier-coated or low-sodium glass require dedicated PID assessment because their leakage-current paths and encapsulant systems differ significantly from conventional designs.
Material-Level Samples
For root-cause analysis, individual solar cells, encapsulant films such as EVA and POE, and front-glass samples can be stressed in dedicated fixtures to isolate the contribution of each material to overall PID resistance.
Testing Items
A complete PID effect analysis experiment evaluates the following parameters before and after the stress exposure:
- Maximum power (Pmax) degradation measured by flash test under Standard Test Conditions (STC)
- Electroluminescence (EL) imaging to visualize shunted cells, dark cross-patterns, and localized defect areas
- Dark I-V characteristic extraction and shunt resistance calculation
- Insulation resistance and wet leakage current testing to confirm electrical safety (IEC 61215 MQT 13 and MQT 15)
- Visual inspection for delamination, corrosion, discoloration, or edge sealing defects
- Optional continuous monitoring of leakage current between the shorted terminals and the grounded frame during stress
- Recovery behavior assessment after open-circuit storage at room temperature or after positive-bias and elevated-temperature treatment
Testing Methods
Sample Preparation and Baseline Characterization
Test samples are first stabilized, visually inspected, and characterized at STC. Baseline I-V curves and EL images are recorded, and initial insulation and wet leakage tests are performed to confirm that the modules are defect-free before stressing.
Environmental and Electrical Stress Application
According to IEC TS 62804-1 and IEC 61215-2 MQT 21, the module output leads are shorted together and a DC voltage of minus 1000 V, or minus 1500 V for modules rated at higher system voltages, is applied between the shorted terminals and the grounded metal frame. The module is held in a climate chamber at 85 degrees Celsius plus or minus 2 degrees and 85 percent relative humidity plus or minus 5 percent for a standard duration of 96 hours. For n-type modules, the worst-case polarity is determined according to the intended inverter grounding scheme. Softer screening conditions, such as 60 degrees Celsius and 85 percent relative humidity with extended duration, may be applied for comparative material studies.
Post-Stress Evaluation and Data Analysis
After the stress period, the module is removed, allowed to dry and stabilize, and then re-characterized under the same conditions as the baseline. The percentage degradation of Pmax is calculated, EL images are compared against baseline images to map the spatial distribution of shunting, and the insulation and wet leakage tests are repeated to verify that no safety-related failure has occurred. If required by the client or certification scheme, the test may be extended by an additional 96 hours to probe long-term stability margins.
Pass and Fail Criteria
The generally accepted pass criterion, as specified in IEC 61215-2, is a maximum power degradation of no more than 5 percent after the full stress sequence, together with successful completion of the post-test insulation and wet leakage requirements and the absence of major visual defects. Modules exceeding this limit, or exhibiting extensive EL darkening concentrated near the frame, are classified as PID-sensitive and require design revision or mitigation measures.
Applications
PID effect analysis experiments serve multiple purposes across the photovoltaic value chain:
- Design verification and certification of new module products within the IEC 61215 and IEC 61730 qualification sequences
- Research and development of anti-PID cell architectures, emitter designs, and silicon nitride anti-reflective coating recipes
- Comparative selection of encapsulants, such as high-resistivity POE versus conventional EVA, and of low-sodium or barrier-coated front glass
- Mass-production quality control and periodic batch screening to detect process drifts that reduce PID resistance
- Bankability reports and technical due diligence for utility-scale projects, particularly those operating at 1500 V
- Field-failure diagnostics for operating power plants, where EL surveys combined with laboratory PID analysis identify degradation sources and support warranty or insurance claims
FAQ
What is the PID effect in solar modules?
PID is a degradation mechanism triggered by the voltage difference between the solar cells and the grounded frame in high-voltage systems. The resulting leakage current transports ions, mainly sodium from the front glass, into the cell structure, where they create shunts and reduce power output.
What are the standard PID test conditions?
The standard procedure applies minus 1000 V DC (or the rated system voltage, such as minus 1500 V) between the shorted module terminals and the grounded frame at 85 degrees Celsius and 85 percent relative humidity for 96 hours, in accordance with IEC TS 62804-1.
How much power degradation is acceptable?
Under IEC 61215-2, a module passes the PID test if maximum power degradation after stress does not exceed 5 percent, provided that insulation, wet leakage, and visual requirements are also met.
Is PID reversible?
Shunting-type PID is largely recoverable: affected modules can regain most of their lost power after extended storage at elevated temperature or after applying a positive bias. Crystal-defect-type PID, however, tends to be permanent, which is why laboratory recovery studies are an important part of a full analysis.
How can PID be prevented?
Effective countermeasures include optimized cell emitters and anti-reflective coatings, high-volume-resistivity encapsulants such as POE, low-sodium or barrier-coated glass, improved edge sealing, and system-level solutions such as charge equalization devices or inverter grounding schemes that limit negative potential.
What is the difference between PID-s, PID-c, and PID-p?
PID-s is the shunting type caused by sodium penetrating the anti-reflective coating, PID-c is the crystal-defect type caused by sodium decorating stacking faults in the silicon, and PID-p is the polarization type associated with charge accumulation at the cell surface, typically under positive bias in certain n-type designs.
Do bifacial and double-glass modules need PID testing?
Yes. Although double-glass and frameless constructions change the leakage-current paths, they remain exposed to system voltage stress, and IEC TS 62804-1 provides dedicated procedures for evaluating modules without conventional grounded frames.