IC substrate coefficient of thermal expansion (CTE) curve determination is a critical thermomechanical characterization technique used to evaluate the dimensional stability of package substrates across operating and reflow temperature ranges. By measuring the expansion curve through methods such as thermomechanical analysis (TMA), engineers can extract the CTE below and above the glass transition temperature (Tg), enabling accurate warpage prediction, solder joint reliability assessment, and material qualification for advanced packaging applications.
Technical Overview
The coefficient of thermal expansion (CTE) curve of an IC substrate describes how the substrate dimensions change as a function of temperature, typically from room temperature up to 260 °C or beyond. Because an IC package is a stack-up of materials with very different expansion behaviors—silicon die at approximately 2.6–3.2 ppm/°C, organic substrate cores at 12–17 ppm/°C, and build-up dielectric films at 20–90 ppm/°C—thermal expansion mismatch is one of the dominant drivers of warpage, solder joint fatigue, copper trace cracking, and interfacial delamination.
A typical CTE curve exhibits two distinct linear regions separated by a transition zone. The slope below the glass transition temperature is defined as α1 (CTE below Tg), while the slope above the transition is α2 (CTE above Tg). The inflection point of the expansion curve provides the Tg value determined by thermomechanical analysis (TMA Tg), which often differs from the Tg measured by DSC or DMA. For through-thickness (z-axis) measurements, α2 can reach 40–200 ppm/°C for epoxy-based and ABF-based substrates, making z-expansion a key concern for via and microvia reliability.
IC substrate CTE curve determination is routinely performed during material incoming inspection, new substrate qualification, supplier benchmarking, warpage simulation model validation, and failure analysis. Standards such as IPC-TM-650 2.4.24 and ASTM E831 govern the most widely used test procedures in the electronics packaging industry.
Testing Samples
Rigid Core Substrates (BT and Epoxy Cores)
Bismaleimide triazine (BT) resin and epoxy-glass core substrates are the most common core materials for BGA and memory substrates. Samples are typically cut into strips or discs of 4–10 mm, with thicknesses from 100 to 800 μm. Both glass-fabric-reinforced laminates and copper-clad variants can be tested, with copper either etched away or retained depending on whether the dielectric or composite response is required.
Build-up Dielectric Films (ABF and Photoimageable Dielectrics)
Ajinomoto Build-up Film (ABF) and other build-up dielectrics are laminated and cured on carriers, then tested as free-standing films or as cured laminates to capture their high expansion behavior. Because these films dominate z-axis expansion in fine-line substrates, their CTE curves above Tg are of particular importance for microvia reliability in flip-chip and 2.5D/3D packages.
Glass Core and Inorganic Substrate Materials
Glass cores, glass-ceramic hybrids, and silicon interposers offer CTE values close to that of the silicon die (3–9 ppm/°C). Their CTE curves are determined with high-resolution methods because the expansion magnitudes are small and the measurement uncertainty budget is correspondingly tighter.
Finished Multilayer Substrates and Coupons
Complete substrate stacks—core, build-up layers, copper redistribution, solder mask, and embedded passives—can be tested to obtain the effective composite CTE curve. Panel-level process coupons and finished package substrates are commonly evaluated in both x/y (in-plane) and z (out-of-plane) orientations to validate warpage simulation inputs.
Testing Items
- Full thermal expansion curve (ΔL/L0 versus temperature) over the specified temperature range, typically 25–260 °C or 25–300 °C.
- α1: coefficient of thermal expansion below Tg, usually calculated between 50 °C and 150 °C or another specified window.
- α2: coefficient of thermal expansion above Tg, calculated from the second linear region following the transition knee.
- Tg by TMA: glass transition temperature identified from the inflection point of the expansion curve.
- Percent expansion at reflow temperature (e.g., ΔL/L at 245 °C or 260 °C), directly relevant to warpage during assembly.
- In-plane (x/y) CTE versus out-of-plane (z) CTE, since glass fabric reinforcement creates strong anisotropy.
- Comparison of first and second heating scans to reveal curing history, residual stress relaxation, and moisture effects.
Testing Methods
Thermomechanical Analysis (TMA)
TMA is the industry-standard technique for z-axis CTE curves of IC substrates. A low-mass quartz probe applies a small static force (typically 0.05–0.20 N) on the sample surface while a furnace ramps the temperature at 3–10 °C/min under nitrogen. Dimensional change is recorded with a resolution of tens of nanometers, and α1, α2, and TMA Tg are extracted from the expansion curve per ASTM E831 and IPC-TM-650 2.4.24. Flat, parallel specimens and proper calibration with a certified reference material (such as fused silica or aluminum) are essential for accuracy.
Horizontal Dilatometry
Push-rod dilatometry per ASTM E228 measures in-plane expansion of strip specimens with excellent accuracy over wide temperature ranges. It is frequently used for x/y CTE determination of core laminates and for cross-checking TMA results on anisotropic materials.
Strain Gauge Method
Foil strain gauges bonded to substrate coupons allow in-plane CTE measurement of large panels and finished substrates, including temperature cycling between −55 °C and 250 °C. The method is covered by IPC-TM-650 2.4.41 and is well suited for evaluating effective CTE of complex multilayer stack-ups.
Interferometric and Optical Methods
Laser interferometry per ASTM E289 and full-field optical techniques such as digital image correlation (DIC), shadow moiré, and 3D digital microscopy provide non-contact CTE and warpage mapping. DIC is increasingly used to measure local CTE gradients across substrate features, build-up layers, and hyperbolically graded regions, while shadow moiré measures full-field out-of-plane deformation during simulated reflow.
Test Procedure and Data Reduction
A typical protocol includes: specimen preparation to specified dimensions with ground parallel faces; baking to remove moisture (for example, 105 °C for 1–2 hours) unless the as-received condition is of interest; dimensional metrology at 23 ± 2 °C; instrument calibration and baseline correction with an empty-pan or reference run; controlled heating under nitrogen; and secant or tangent slope calculation over defined temperature windows. A second heating cycle is recommended to separate irreversible effects (cure continuation, stress relief, moisture loss) from the intrinsic reversible expansion behavior.
Applications
- Warpage simulation and mitigation for flip-chip BGA, chip-scale packages, and large-body server substrates, where accurate α1, α2, and Tg inputs determine finite-element model fidelity.
- Solder joint reliability prediction during thermal cycling (−40 °C to 125 °C) and reflow (up to 260 °C), where CTE mismatch between die, substrate, and board drives fatigue damage models such as Coffin–Manson analysis.
- Material qualification and supplier comparison of BT cores, ABF build-up films, epoxy resins, solder masks, and emerging glass cores against specifications such as IPC-4101 and customer-specific datasheets.
- New product introduction for advanced packaging formats, including 2.5D interposers, 3D stacked packages, chiplet integration, and panel-level packaging, where tight CTE control is mandatory.
- Process monitoring after lamination, curing, desmear, and multiple reflow exposures, detecting cure drift or thermal degradation through shifts in Tg and α2.
- Failure analysis of delamination, microvia cracking, and copper trace fracture, where reconstructed expansion curves help confirm whether thermal expansion mismatch exceeded design allowables.
FAQ
Why do z-axis and x/y CTE values differ so much on the same substrate?
Glass fabric reinforcement constrains expansion in the in-plane directions, typically yielding x/y CTE of 10–17 ppm/°C, while the resin-rich through-thickness direction is far less constrained and can expand at 40–200 ppm/°C above Tg. This anisotropy is intrinsic to composite substrate construction and must be measured in both orientations.
Which temperature range and heating rate should be used?
For most IC substrate work, 25 °C to 260 °C at 5 °C/min under nitrogen is standard because it spans the full reflow profile. IPC-TM-650 2.4.24 commonly references 5 °C/min, and slower rates improve transition resolution, while faster rates can shift the apparent Tg. The chosen conditions should always be reported with the results.
Why does TMA Tg differ from DSC Tg?
TMA Tg is detected through the change in mechanical expansion behavior, whereas DSC detects the change in heat capacity. The two techniques respond to different manifestations of the glass transition and can differ by 5–20 °C. For substrate warpage and dimension-driven problems, TMA Tg is generally the more relevant value.
How should samples be prepared to ensure accurate curves?
Specimens must have flat, parallel faces free of burrs and residual stress from cutting. Moisture should be controlled by pre-baking unless the as-received state is being evaluated, and an initial conditioning or first-heat scan is useful to remove thermal history. Certified reference materials should be run regularly to validate probe calibration.
What CTE values are typical for common substrate materials?
BT/epoxy glass cores typically show α1 of 12–16 ppm/°C in-plane; ABF build-up films show α1 of 20–45 ppm/°C and α2 of 80–150 ppm/°C in the z-axis; glass cores range from 3 to 9 ppm/°C; and silicon is approximately 2.6–3.2 ppm/°C. Matching substrate CTE between that of the die and the printed circuit board minimizes package-level thermomechanical stress.